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Showing results 1 to 6 of 6
Conference
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

ISSCC2008, 2008-02-04

Conference
A Crosstalk-and-ISI Equalizing Receiver in 2-Drop Single-Ended SSTL Memory Channel

CICC, 2010-09-19

Conference
A Crosstalk-and-ISI Equalizing Receiver in 2-Drop Single-Ended SSTL Memory Channel

IEEE Custom Integrated Circuits Conference, 2010-09-21

Conference
A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using a Three-Level Balanced Coding Scheme

2016 Symposia on VLSI Technology and Circuits, 2016-06-15

Conference
A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using a Three-Level Balanced Coding Scheme

2016 Symposia on VLSI Technology and Circuits, 2016-06-15

Thesis
Equalization 기법의 멀티 드롭 단일 신호선 2~5Gbs DRAM 인터페이스 회로

Thesis(Doctor), 2005

1
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