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Showing results 1 to 7 of 7
Thesis
A 3.8Gbps DRAM DFE-Receiver Circuit with a Single-Loop SS-LMS Algorithm and a 2Gbps LCD Intra-Panel interface circuit with VSYNC-Embedded Clock

Thesis(Doctor), 2011

Conference
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

ISSCC2008, 2008-02-04

Conference
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

IEEE International Solid-State Circuits Conference, 2008-02-03

Conference
A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

Society for Information Display 2010, page. 62 - 65, 2010-05-25

Conference
A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

SID Symposium Digest of Technical Papers, 2010-05-30

Thesis
Digital Versatile Disk 및 Blue-laser Disk 용 CMOS Multi-phase Delay-Locked Loop

Thesis(Master), 2005

Conference
The BLADE-ON PETIOLE gene is required for maintenance of the determinats state of organs in Arabidopsis

XIII International Conference on Arabidopsis Research, 2002-06-28

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