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Conference

64bit RISC-V 기반 칩 검증 플랫폼 설계

제 29회 한국반도체학술대회, 2022-01-25

Article

Layerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural NetworkSCOPUS

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 40, no. 1, page. 1 - 10, 2021-01

Conference

Rapid design space exploration of near-optimal memory-reduced DCNN architecture using multiple model compression techniques

53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, 2021-05-23

Conference

Sparsity-aware memory interface architecture using stacked XORNet compression for accelerating pruned-DNN models

6th Conference on Machine Learning and Systems (MLSys), 2023-06-05

Conference

Sparsity-aware memory interface architecture using stacked XORNet compression for accelerating pruned-DNN models

6th Conference on Machine Learning and Systems (MLSys), 2023-06-05

1

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