A low-power half-swing clocking scheme for flip-flop with complementary gate and source drive

Abstract

A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS hip-flop to reduce the power consumption of the clock system by 43%, while keeping the hip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-hop using this scheme is less than half of that using the previous half-swing clocking scheme.