A compact radix-64 54 x 54 CMOS redundant binary parallel multiplier

Abstract

The radix-64 encoding scheme was used to reduce the number of partial products in the 54 x 54 CMOS parallel multiplier, The transistor counts the chip area and the power-delay product were reduced by 28%, 22%, and 17%, respectively. compared to any of the published 51 x 54 CMOS parallel multipliers. A redundant binary (RB) number system was used to represent any of the 65 multiplying coefficients as a RB number which consists of two of 9 fundamental multiplying coefficients and their complements. The resultant RB partial products were added by using optimized RB adders. The total transistor count of the proposed multiplier was 43,579. The chip area in 0.25 mum CMOS process with 5 metal layers was 0,99 mm(2). The power consumption and the multiplication time were 111 mW and 6.9 ns. respectively.