DC Field | Value | Language |
---|---|---|
dc.contributor.author | Heo, SC | - |
dc.contributor.author | Jang, YC | - |
dc.contributor.author | Park, SH | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2015-06-25T02:00:14Z | - |
dc.date.available | 2015-06-25T02:00:14Z | - |
dc.date.created | 2009-02-28 | - |
dc.date.issued | 2003-04 | - |
dc.identifier.issn | 0916-8524 | - |
dc.identifier.other | 2015-OAK-0000003317 | en_US |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/10282 | - |
dc.description.abstract | An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-mum double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal. | - |
dc.description.statementofresponsibility | open | en_US |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION CO | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.rights | BY_NC_ND | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/2.0/kr | en_US |
dc.title | An 8-bit 200 MS/s CMOS folding/interpolating analog-to-digital converter | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | en_US |
dc.author.google | Heo, SC | en_US |
dc.author.google | Jang, YC | en_US |
dc.author.google | Park, HJ | en_US |
dc.author.google | Park, SH | en_US |
dc.relation.volume | E86C | en_US |
dc.relation.issue | 4 | en_US |
dc.relation.startpage | 676 | en_US |
dc.relation.lastpage | 681 | en_US |
dc.contributor.id | 10071836 | en_US |
dc.relation.journal | IEICE TRANSACTIONS ON ELECTRONICS | en_US |
dc.relation.index | SCI급, SCOPUS 등재논문 | en_US |
dc.relation.sci | SCIE | en_US |
dc.collections.name | Journal Papers | en_US |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E86C, no.4, pp.676 - 681 | - |
dc.identifier.wosid | 000182025800022 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 681 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 676 | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E86C | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.identifier.scopusid | 2-s2.0-0142248304 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 2 | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | REDUCED NUMBER | - |
dc.subject.keywordPlus | A/D CONVERTER | - |
dc.subject.keywordPlus | ADC | - |
dc.subject.keywordAuthor | analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | resistor averaging | - |
dc.subject.keywordAuthor | folding | - |
dc.subject.keywordAuthor | interpolating | - |
dc.subject.keywordAuthor | differential logic | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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