A decision feedback equalizing receiver for the SSTL SDRAM interface with clock-data skew compensation
SCIE
SCOPUS
- Title
- A decision feedback equalizing receiver for the SSTL SDRAM interface with clock-data skew compensation
- Authors
- Sohn, YS; Bae, SJ; Park, HJ; Cho, SI
- Date Issued
- 2004-05
- Publisher
- IEICE-INST ELECTRONICS INFORMATION CO
- Abstract
- A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF x 4 stub load. Active chip area and power consumption are 300 x 1000 mum(2) and 142 mW, respectively, with a 2.5 V, 0.25 mum CMOS process.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/10285
- ISSN
- 0916-8524
- Article Type
- Article
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, vol. E87C, no. 5, page. 809 - 817, 2004-05
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