DC Field | Value | Language |
---|---|---|
dc.contributor.author | Nam, JJ | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2015-06-25T02:00:28Z | - |
dc.date.available | 2015-06-25T02:00:28Z | - |
dc.date.created | 2009-02-28 | - |
dc.date.issued | 2005-04 | - |
dc.identifier.issn | 0916-8524 | - |
dc.identifier.other | 2015-OAK-0000005035 | en_US |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/10287 | - |
dc.description.abstract | An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 50 +/- 0.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively. | - |
dc.description.statementofresponsibility | open | en_US |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION CO | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.rights | BY_NC_ND | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/2.0/kr | en_US |
dc.title | An all-digital CMOS duty cycle correction circuit with a duty-cycle correction range of 15-to-85% for multi-phase applications | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | en_US |
dc.identifier.doi | 10.1093/ietele/e88-c.4.773 | - |
dc.author.google | Nam, JJ | en_US |
dc.author.google | Park, HJ | en_US |
dc.relation.volume | E88C | en_US |
dc.relation.issue | 4 | en_US |
dc.relation.startpage | 773 | en_US |
dc.relation.lastpage | 777 | en_US |
dc.contributor.id | 10071836 | en_US |
dc.relation.journal | IEICE TRANSACTIONS ON ELECTRONICS | en_US |
dc.relation.index | SCI급, SCOPUS 등재논문 | en_US |
dc.relation.sci | SCIE | en_US |
dc.collections.name | Journal Papers | en_US |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E88C, no.4, pp.773 - 777 | - |
dc.identifier.wosid | 000228413000049 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 777 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 773 | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E88C | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.identifier.scopusid | 2-s2.0-33645562273 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 9 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | duty cycle correction | - |
dc.subject.keywordAuthor | all-digital | - |
dc.subject.keywordAuthor | multi-phase clock | - |
dc.subject.keywordAuthor | PLL/DLL | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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