DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, SH | - |
dc.contributor.author | Kim, JC | - |
dc.contributor.author | Jung, SW | - |
dc.contributor.author | Jeong, YH | - |
dc.date.accessioned | 2015-06-25T02:00:52Z | - |
dc.date.available | 2015-06-25T02:00:52Z | - |
dc.date.created | 2010-05-07 | - |
dc.date.issued | 2008-05 | - |
dc.identifier.issn | 0916-8524 | - |
dc.identifier.other | 2015-OAK-0000007863 | en_US |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/10295 | - |
dc.description.abstract | This study describes the dependence of the surface electric field to the junction depth of source/drain-extension, and the suppression of gate induced drain leakage (GIDL) in fully depleted shallow junction gate-overlapped source/drain-extension (SIDE). The GIDL can be reduced by reducing shallow junction depth of drain-extension. Total space charges are a function of junction depth in fully depleted shallow junction drain-extension, and the surface potential is proportional to these charges. Because the GIDL is proportional to surface potential, GIDL is the function of junction depth in fully depleted shallow junction drain-extension. Therefore, the GIDL is suppressed in a fully depleted shallow junction drain-extension by reducing surface potential. Negative substrate bias and halo doping could suppress the GIDL, too. The GIDL characteristic under negative substrate bias is contrary to other GIDL models. | - |
dc.description.statementofresponsibility | open | en_US |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.rights | BY_NC_ND | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/2.0/kr | en_US |
dc.title | Junction depth dependence of the gate induced drain leakage in shallow junction source/drain-extension nano-CMOS | - |
dc.type | Article | - |
dc.contributor.college | 단일계열 | en_US |
dc.identifier.doi | 10.1093/IETELE/E91-C.5.761 | - |
dc.author.google | Song, SH | en_US |
dc.author.google | Kim, JC | en_US |
dc.author.google | Jeong, YH | en_US |
dc.author.google | Jung, SW | en_US |
dc.relation.volume | E91-C | en_US |
dc.relation.issue | 5 | en_US |
dc.relation.startpage | 761 | en_US |
dc.relation.lastpage | 766 | en_US |
dc.contributor.id | 10106021 | en_US |
dc.relation.journal | IEICE TRANSACTIONS ON ELECTRONICS | en_US |
dc.relation.index | SCI급, SCOPUS 등재논문 | en_US |
dc.relation.sci | SCI | en_US |
dc.collections.name | Journal Papers | en_US |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E91-C, no.5, pp.761 - 766 | - |
dc.identifier.wosid | 000256861500018 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 766 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 761 | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E91-C | - |
dc.contributor.affiliatedAuthor | Jeong, YH | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 2 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | GIDL | - |
dc.subject.keywordAuthor | junction | - |
dc.subject.keywordAuthor | halo | - |
dc.subject.keywordAuthor | nanoscale CMOS | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
library@postech.ac.kr Tel: 054-279-2548
Copyrights © by 2017 Pohang University of Science ad Technology All right reserved.