DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jae-seung Lee | - |
dc.contributor.author | SIM, JAE YOON | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2015-06-25T02:01:03Z | - |
dc.date.available | 2015-06-25T02:01:03Z | - |
dc.date.created | 2010-12-02 | - |
dc.date.issued | 2010-08 | - |
dc.identifier.issn | 0916-8524 | - |
dc.identifier.other | 2015-OAK-0000022141 | en_US |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/10299 | - |
dc.description.abstract | A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10 mu m and L = 0.18 mu m in a 16 x 16 array matrix fabricated with a 0.18-mu m process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7 mV and 32.2 mV, respectively, for the temperature range from -25 degrees C to 75 degrees C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10 mV/bit and 3.53 mV/bit at 25 degrees C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125 ns, which corresponds to the 8-MHz throughput. | - |
dc.description.statementofresponsibility | open | en_US |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.rights | BY_NC_ND | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/2.0/kr | en_US |
dc.title | A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | en_US |
dc.identifier.doi | 10.1587/TRANSELE.E93.C.1333 | - |
dc.author.google | Lee, JS | en_US |
dc.author.google | Sim, JY | en_US |
dc.author.google | Park, HJ | en_US |
dc.relation.volume | E93C | en_US |
dc.relation.issue | 8 | en_US |
dc.relation.startpage | 1333 | en_US |
dc.relation.lastpage | 1337 | en_US |
dc.contributor.id | 10100874 | en_US |
dc.relation.journal | IEICE TRANSACTIONS ON ELECTRONICS | en_US |
dc.relation.index | SCI급, SCOPUS 등재논문 | en_US |
dc.relation.sci | SCIE | en_US |
dc.collections.name | Journal Papers | en_US |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.8, pp.1333 - 1337 | - |
dc.identifier.wosid | 000281341900020 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 1337 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1333 | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E93C | - |
dc.contributor.affiliatedAuthor | SIM, JAE YOON | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 1 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | on-chip variation monitoring | - |
dc.subject.keywordAuthor | threshold voltage | - |
dc.subject.keywordAuthor | time-to-digital converter (TDC) | - |
dc.subject.keywordAuthor | voltage controlled delay line (VCDL) | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
library@postech.ac.kr Tel: 054-279-2548
Copyrights © by 2017 Pohang University of Science ad Technology All right reserved.