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Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array

Title
Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array
Authors
JINSEOK, KIMJONGEUN, KOOTAESU, KIMYUL, HWA KIMHYUNGJUN, KIMYOOSEUNGHYUNKIM, JAE JOON
Date Issued
2019-06-12
Publisher
IEEE
URI
https://oasis.postech.ac.kr/handle/2014.oak/103461
Article Type
Conference
Citation
Symposium on VLSI Circuits, 2019-06-12
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김재준KIM, JAE JOON
Dept. Convergence IT Engineering
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