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dc.contributor.authorKANG, BONG KOO-
dc.contributor.authorYeohyeok Yun-
dc.contributor.authorJi-Hoon Seo-
dc.date.accessioned2020-04-17T01:51:29Z-
dc.date.available2020-04-17T01:51:29Z-
dc.date.created2020-04-16-
dc.date.issued2019-11-19-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/103483-
dc.publisherIWDTF 2019-
dc.relation.isPartOfIWDTF 2019-
dc.relation.isPartOfProceeding on IWDTF-
dc.titleAnalysis of Positive Bias Temperature Instability Degradation in n+ and p+ poly-Si Gates of High-Voltage SiO2 Dielectric nMOSFETs-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitationIWDTF 2019-
dc.citation.conferenceDate2019-11-18-
dc.citation.conferencePlaceJA-
dc.citation.titleIWDTF 2019-
dc.contributor.affiliatedAuthorKANG, BONG KOO-
dc.contributor.affiliatedAuthorYeohyeok Yun-
dc.description.journalClass1-
dc.description.journalClass1-

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강봉구KANG, BONG KOO
Dept of Electrical Enginrg
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