High-Level Statistical Static Timing Analysis and Optimization

Abstract

The variations of process parameters have increased due to the continued scaling down of semiconductor process technology. Process parameter variation has been expected as a bottleneck in the sub-100nm CMOS technology. Large process parameter variation induces serious variation of circuit performance and leads to the yield degradation. It is necessary to alleviate, predict and analyze the impact of these process variations on integrated circuits for future generations of MOSFET technology. In particular, the circuit timing is known to be very sensitive to the process variations among the circuit characteristics. Therefore, it needs to accurately analyze the circuit timing on the effects of process variations and to reflect them in the chip design. Well-known conventional timing analysis methods considering the process variations are the worst case corner-based analysis and the Monte-Carlo simulation-based analysis. The worst case corner-based analysis method has been widely used as a good approach to consider process variations for the timing analysis. Unfortunately, this approach pessimistically estimates the timing yield for recent technology with small feature sizes, because the intra-die variation becomes comparable to the inter-die variation. The Monte-Carlo simulation-based analysis can obtain a relatively accurate estimate of the timing distribution, but this method is computationally expensive. To effectively consider the process variation, a statistical static timing analysis (SSTA) has been proposed. With the increase of the design complexity, a demand for the high-level design has increased. In spite of these needs, current researches on statistical approaches are mostly focused on gate level. Recently, a few statistical timing analysis methods for high level synthesis (HLS) have been proposed. However, these methods do not consider some important factors such as correlations among resources, and thus, these methods have an accurate problem. To accurately estimate the circuit timing, therefore, this thesis proposes a novel high-level SSTA method. In addition, this thesis proposes a promising resource binding algorithm for maximizing the timing yield for high-level synthesis. First, the proposed high-level SSTA method uses timing information of resources from an existing gate-level SSTA technique. Based on a high-level design description, such as a date flow graph (DFG), the timing graph is built and statistically analyzed. The proposed timing graph describes the timing quantity of each resource, which is normalized to one clock period. The proposed method can accept various hardware implementation techniques and can consider correlations among resources. It analytically evaluates the circuit timing distribution, and then analyzes the circuit timing yield over a given timing constraints. In experiments using the digital signal processing (DSP) benchmark circuits, the proposed method estimated the relatively accurate timing yields, compared to the Monte-Carlo simulation-based analysis (MC-sim) well-known as an accurate method: average relative errors are 2.5%

95% , 0.63%

99% , and 0.07%

99.87% (3σ) (the subscripts mean the timing yields of MC-sim).Second, the proposed resource binding algorithm targets to maximize the timing yield of a chip under a given area constraint. The proposed algorithm uses some critical modules, identified using the timing yield criticality, as the candidate modules for the module reselection. In the resource library, the candidate modules are replaced with new modules, which are dissimilar size and performance and which can improve the circuit timing yield. The above procedures iteratively improve the circuit timing yield based on the greedy algorithm. In experiments using the DSP benchmark circuits, the proposed algorithm improved the circuit timing yield from 70% to 94.64% and from 80% to 97.22% on average. These results are 4.4% and 2.6% higher than an existing variation-aware resource binding algorithm, proposed by F. Wang et al., with an expense of the circuit area increased by 5%.