Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction

Abstract

Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect portion. We examined the benefits of ternary logic including the impacts of interconnect length reduction using a realistic ternary device model. The standard cell layouts of ternary SUM, NCARRY, NANY, and PROD gates are designed using balanced ternary logic and multi-threshold graphene barrister (MTGB). The interconnect wire length of the 5-trit arithmetic logic unit is reduced by ~37 % and this reduction rate is maintained even in more complex circuits.