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Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion
- Title
- Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion
- Date Issued
- 2020-10
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Abstract
- A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-Trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.
- Article Type
- Conference
- Citation
- 17th International System-on-Chip Design Conference, ISOCC 2020, page. 254 - 255, 2020-10
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