GUI-Enhanced layout generation of FFE SST TXs for fast high-speed serial link design

Abstract

We present the first FFE SST TX layout generator enhanced by various software techniques including a GUI-based template engine. Seven different DRC/LVS-clean TXs were generated in multiple technologies (40nm/65nm/90nm CMOS) for the first time, and achieved adequate maximum data rates: 36Gb/s with 40nm in post-layout simulation; 14Gb/s with 65nm in measurement. Total generation time was less than 5 days, including iterative parameter tuning by a human designer and computation (30 minutes for TX core, 8 hours for power network). Fast post-layout analysis of TX's performance-power trade-off was enabled by the presented generator for the first time.