A Novel In-DRAM Accelerator Architecture for Binary Neural Network

Abstract

We propose a novel computation-in-memory (CIM) architecture based on DRAM for binary neural network, in which a novel charge sharing circuit enables us to perform all logic operations and accumulation inside sub-array at a very small area overhead (1.22%). Especially, the in-DRAM accumulation can significantly reduce off-chip DRAM accesses. Our experiments show that, on VGG-9 model for CIFAR-10, our proposed method, realized on DDR4 DRAM, gives 2.56 times smaller latency per image and 19.57 times lower energy consumption in off-chip data transfer than the existing methods, modified Ambit and DRISA, at a very small accuracy loss (0.23%).