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dc.contributor.authorLEE, JEONG SOO-
dc.contributor.authorJO, YONG JIN-
dc.contributor.authorOH, HYEON GWAN-
dc.contributor.authorYOON, GILSANG-
dc.contributor.authorJIN, JAESEOK-
dc.contributor.authorGO, DONGHYUN-
dc.contributor.authorPARK, JOUNG HUN-
dc.date.accessioned2021-06-01T10:56:14Z-
dc.date.available2021-06-01T10:56:14Z-
dc.date.created2021-03-11-
dc.date.issued2020-02-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/106320-
dc.languageKorean-
dc.publisher한국반도체학술대회-
dc.relation.isPartOf제27회 한국반도체학술대회-
dc.titleEffect of Interface Roughness on Program/Erase Efficiency for 3D Vertical NAND Flash Memory applications-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitation제27회 한국반도체학술대회-
dc.citation.conferenceDate2020-02-12-
dc.citation.conferencePlaceKO-
dc.citation.conferencePlace강원도 하이원리조트-
dc.citation.title제27회 한국반도체학술대회-
dc.contributor.affiliatedAuthorLEE, JEONG SOO-
dc.contributor.affiliatedAuthorJO, YONG JIN-
dc.contributor.affiliatedAuthorOH, HYEON GWAN-
dc.contributor.affiliatedAuthorYOON, GILSANG-
dc.contributor.affiliatedAuthorJIN, JAESEOK-
dc.contributor.affiliatedAuthorGO, DONGHYUN-
dc.contributor.affiliatedAuthorPARK, JOUNG HUN-
dc.description.journalClass2-
dc.description.journalClass2-

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이정수LEE, JEONG SOO
Dept of Electrical Enginrg
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