Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm
- Title
- Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm
- Authors
- Lee, Sung-Yun; Kim, Sunmean; Kang, Seokhyeong
- Date Issued
- 2019-05-23
- Publisher
- IEEE Computer Society
- Abstract
- Logic synthesis has been increasingly important to accelerate the development of high-level systems. However, in multi-valued logic, logic synthesis methods that can process emerging devices are deficient. We propose and automate a method to synthesize ternary logic circuits. Our design of ternary logic circuits is based on static gate design, and exploits carbon nanotube field-effect transistors. We optimize ternary logic circuits by minimizing the number of transistors with a modified Quine-McCluskey algorithm. Our proposed method has improved power-delay product by 52.72 % over the state-of-the-art method for a ternary half adder, and by 68.06 % for a ternary multiplier. We also have improved power-delay product by 37.30 % over the state-of-the-art method for a ternary full adder that has high load capacitance. Our design has an average of 42.43 % fewer transistors than the existing design for circuits that have large number of inputs. As circuits become larger, the improved power-delay product and reduced transistor count are advantageous.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/106446
- Article Type
- Conference
- Citation
- 49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019, page. 158 - 163, 2019-05-23
- Files in This Item:
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.