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Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
- Title
- Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
- Date Issued
- 2019-05-21
- Publisher
- IEEE Computer Society
- Abstract
- We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed ci
- Article Type
- Conference
- Citation
- 49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019, page. 37 - 42, 2019-05-21
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