DC Field | Value | Language |
---|---|---|
dc.contributor.author | He, W. | - |
dc.contributor.author | Yin, S. | - |
dc.contributor.author | Kim, Y. | - |
dc.contributor.author | Sun, X. | - |
dc.contributor.author | Sun, X. | - |
dc.contributor.author | Kim, J. | - |
dc.contributor.author | Yu, S. | - |
dc.contributor.author | Seo, J. | - |
dc.date.accessioned | 2021-09-03T04:06:23Z | - |
dc.date.available | 2021-09-03T04:06:23Z | - |
dc.date.created | 2020-09-10 | - |
dc.date.issued | 2020-07 | - |
dc.identifier.issn | 2573-9603 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/106914 | - |
dc.description.abstract | In-memory computing (IMC) has emerged as a promising technique for enhancing energy-efficiency of deep neural networks (DNN). While embedded non-volatile memory such as resistive RAM (RRAM) is a good alternative to SRAM/ DRAM for IMC owing to high density, low leakage, and non-destructive read, most prior works have not demonstrated using multi-level RRAM devices for array-level IMC operations. In this work, we present an IMC prototype with 2-bit-per-cell RRAM devices for area-/energy-efficient DNN inference. Optimizations on four-level conductance distribution and peripheral circuits with input-splitting scheme have been performed, enabling high DNN accuracy and low area/energy consumption. The prototype chip that monolithically integrated 90nm CMOS and 2-bit-per-cell RRAM array achieves 87% (83%) CIFAR-10 accuracy and 25 (51) TOPS/W energy-efficiency at 1.2 V (0.9 V) supply. At 1.2V, a stable accuracy of 87% is maintained throughout 108 hours. IEEE | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | IEEE Solid-State Circuits Letters | - |
dc.title | 2-Bit-per-Cell RRAM based In-Memory Computing for Area-/Energy-Efficient Deep Learning | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LSSC.2020.3010795 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE Solid-State Circuits Letters, v.3, pp.194 - 197 | - |
dc.citation.endPage | 197 | - |
dc.citation.startPage | 194 | - |
dc.citation.title | IEEE Solid-State Circuits Letters | - |
dc.citation.volume | 3 | - |
dc.contributor.affiliatedAuthor | Kim, Y. | - |
dc.contributor.affiliatedAuthor | Kim, J. | - |
dc.identifier.scopusid | 2-s2.0-85089296649 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Deep neural networks | - |
dc.subject.keywordAuthor | Energy efficiency | - |
dc.subject.keywordAuthor | in-memory computing | - |
dc.subject.keywordAuthor | multi-level cell | - |
dc.subject.keywordAuthor | Neural networks | - |
dc.subject.keywordAuthor | Programming | - |
dc.subject.keywordAuthor | Prototypes | - |
dc.subject.keywordAuthor | Resistance | - |
dc.subject.keywordAuthor | RRAM. | - |
dc.subject.keywordAuthor | Semiconductor device measurement | - |
dc.subject.keywordAuthor | Solid state circuits | - |
dc.description.journalRegisteredClass | scopus | - |
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