Ternary Sense Amplifier Design for Ternary SRAM

Abstract

This paper proposes the design of a Ternary Sense Amplifier (T-SA) using Samsung-28nm fabrication process that can sense three states, which are VDD, VDD/2, and GND. The T-SA has a ternary inverter back-To-back structure, and is configured as a latch type. The trade-off relationship between sensing margin and sensing speed was analyzed according to the size. The T-SA may enable the realization of a memory array with ternary logic in a Multi-Valued Logic system.