FPGA Implementation of USB 2.0 Serail Interface Engine Chip Using Verilog

Abstract

This research implements USB 2.0 Serial Interface Engine (SIE) using Verilog. The implemented SIE consists of packet disassembly, protocol engine and packet assembly. The implemented SIE verifies the correct operation using input pattern of IN/OUT Transaction, thereby checking Token, Data, Handshake packet identification, Data packet Generation, Handshake packet Generation, CRC checking and Generation. The SIE is implemented on Xilinx Virtex-5 FPGA chip and uses 8775 gates. To behavioral simulate, NC-verilog simulator is used. To synthesis and post simulate, ISE software program is used.