A 87.5-dB-SNDR Residue-integrated SAR ADC with a Digital-domain Capacitor Mismatch Calibration

Abstract

This paper presents an asynchronous-clocking 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) suitable for high-precision sensor applications. Comparator noise and nonlinearity from capacitor mismatch, as two major performance-limiting problems of SAR ADC, are resolved by noise averaging with a residue integration and a digital-domain capacitor error calibration, respectively. The proposed ADC is implemented using 180-nm CMOS technology in an area of 0.68㎟. The calibration improves SNDR by 5.9 dB and SFDR by 14.3 dB, achieving an SNDR of 87.5 dB and an SFDR of 106.85 dB, respectively.