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dc.contributor.authorCHANGHYEON, KIMCHANGHYEON-
dc.contributor.authorRIM, DONGYOUNG-
dc.contributor.authorJEONGWON, CHOE-
dc.contributor.authorKAM, DONG YUN-
dc.contributor.authorPark, Giyoon-
dc.contributor.authorKim, Seokki-
dc.contributor.authorLEE, YOUNGJOO-
dc.date.accessioned2022-03-03T05:40:55Z-
dc.date.available2022-03-03T05:40:55Z-
dc.date.created2022-03-03-
dc.date.issued2021-11-08-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/110209-
dc.description.abstractThe ordered statistic decoding (OSD) approach for short-length BCH codes has been continuously considered as one of the promising error-correction codes by achieving a block error rate (BLER) of less than 10^{-6}, which is attractive to the ultra-reliable and low-latency communication (URLLC) for industrial IoT (IIOT) solutions [1], [2]. However, it is hard to directly realize the conventional OSD algorithm because of the compute-intensive Gaussian elimination and iterative reprocessing steps. Based on the recent segmentation discarding decoding (SDD) approach [3], in this work, we newly present an ultralow-latency OSD architecture reducing the decoding latency by 12 times, which is implemented at an FPGA-based verification platform.-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.relation.isPartOf2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021-
dc.relation.isPartOfProceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference-
dc.titleFPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitation2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021-
dc.identifier.wosid000768220800011-
dc.citation.conferenceDate2021-11-07-
dc.citation.conferencePlaceKO-
dc.citation.conferencePlaceBusan, SOUTH KOREA-
dc.citation.title2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021-
dc.contributor.affiliatedAuthorCHANGHYEON, KIMCHANGHYEON-
dc.contributor.affiliatedAuthorRIM, DONGYOUNG-
dc.contributor.affiliatedAuthorJEONGWON, CHOE-
dc.contributor.affiliatedAuthorKAM, DONG YUN-
dc.contributor.affiliatedAuthorPark, Giyoon-
dc.contributor.affiliatedAuthorLEE, YOUNGJOO-
dc.description.journalClass1-
dc.description.journalClass1-

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이영주LEE, YOUNGJOO
Dept of Electrical Enginrg
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