DC Field | Value | Language |
---|---|---|
dc.contributor.author | CHANGHYEON, KIMCHANGHYEON | - |
dc.contributor.author | RIM, DONGYOUNG | - |
dc.contributor.author | JEONGWON, CHOE | - |
dc.contributor.author | KAM, DONG YUN | - |
dc.contributor.author | Park, Giyoon | - |
dc.contributor.author | Kim, Seokki | - |
dc.contributor.author | LEE, YOUNGJOO | - |
dc.date.accessioned | 2022-03-03T05:40:55Z | - |
dc.date.available | 2022-03-03T05:40:55Z | - |
dc.date.created | 2022-03-03 | - |
dc.date.issued | 2021-11-08 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/110209 | - |
dc.description.abstract | The ordered statistic decoding (OSD) approach for short-length BCH codes has been continuously considered as one of the promising error-correction codes by achieving a block error rate (BLER) of less than 10^{-6}, which is attractive to the ultra-reliable and low-latency communication (URLLC) for industrial IoT (IIOT) solutions [1], [2]. However, it is hard to directly realize the conventional OSD algorithm because of the compute-intensive Gaussian elimination and iterative reprocessing steps. Based on the recent segmentation discarding decoding (SDD) approach [3], in this work, we newly present an ultralow-latency OSD architecture reducing the decoding latency by 12 times, which is implemented at an FPGA-based verification platform. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 | - |
dc.relation.isPartOf | Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference | - |
dc.title | FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 | - |
dc.identifier.wosid | 000768220800011 | - |
dc.citation.conferenceDate | 2021-11-07 | - |
dc.citation.conferencePlace | KO | - |
dc.citation.conferencePlace | Busan, SOUTH KOREA | - |
dc.citation.title | 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 | - |
dc.contributor.affiliatedAuthor | CHANGHYEON, KIMCHANGHYEON | - |
dc.contributor.affiliatedAuthor | RIM, DONGYOUNG | - |
dc.contributor.affiliatedAuthor | JEONGWON, CHOE | - |
dc.contributor.affiliatedAuthor | KAM, DONG YUN | - |
dc.contributor.affiliatedAuthor | Park, Giyoon | - |
dc.contributor.affiliatedAuthor | LEE, YOUNGJOO | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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