Method for measuring deep levels in thin silicon-on-insulator layer without any interface effects

Abstract

A method for accurate measurement of deep levels in a thin silicon-on-insulator (SOI) layer by the capacitance deep level transient spectroscopy (DLTS) is proposed. The proposed method uses a vertical capacitor structure consisting of a Schottky contact, an n-type SOI layer, a buried oxide (BOX) layer, a p-type substrate silicon layer, and a back-side ohmic contact. With this structure, the high series resistance problems inherent in a horizontal SOI capacitor structure are reduced and the charge coupling problems inherent in a conventional vertical SOI capacitor structure are solved by biasing both interfaces of the BOX layer into the accumulation region. Also, the bulk properties of the SOI layer are decoupled from the effects of surface traps by the space-charge region formed at the Schottky contact. For a thin SOI layer fabricated with medium dose oxygen ion implantation, two distinct deep levels are observed at the levels of 0.33 and 0.40 eV below the conduction bandedge with corresponding concentrations of 1.6 x 10(16) and 1.2 x 10(16) cm(-3), respectively. From experimental data and comparison with other reported deep levels, it is concluded that the oxygen implantation induced crystalline defects are responsible for the source of these deep levels.