3D NAND 메모리에서 P / E 사이클링 스트레스 후 트랩 분포 연구

Abstract

Recently, three-dimensional (3-D) NAND Flash Memory has been continuously scaled down to further increase its density and manufacturing cost. The band engineering layer (BE) in 3-D NAND was generally introduced to enhance program speed without degrading reliability. However, even NAND with BE layer has been still sufferred from the trap generation especially when program/erase (P/E) cycling was performed. Accurate method of extracting traps in BE layers have necessitated in order to understand trap generation and charge loss mechanism in scaled 3-D NAND devices. Here, we extracted trap profiling in BE layers of 3-D NAND flash after P/E cycling stress using trap spectroscopy by charge injection and sensing (TSCIS) method. The trap profiling of the tunneling layer was extracted and compared both from SS and GS before and after P/E cycling stress. The trap generation was more significant in SS. The average trap density was increased by 30 % at 2.6 nm from the poly-Si /tunneling layer interface, and by 28% at EC  ET = 1.6 eV, respectively. In GS case, relatively small variaiton of trap density was oberved after the P/E stress. The trap profiling in 3-D NAND memory has successfully demonstrated. The trap profiling could be very useful to evaluate the robustness of bandgap engineerd dielectric layers in developing next flash devices with further scaling.