A Study on Vertical 3D NAND Flash Memory and Vacuum Channel Field-Emission Transistors using Technical Computer-Aided Design (TCAD) Simulation

Abstract

Technical Computer-Aided Design (TCAD) is very useful to predict electrical performances in various device applications. Especially, in a semiconductor industry, TCAD simulation is more powerful tool to investigate electrical characteristics, physical mechanism, and failure mechanism without fabrication of devices, which becomes more and more attractive as considering the nanoscale miniaturization and the complexity of fabrication technology. In this study, advanced semiconductor devices such as 3D Vertical NAND flash memory (V-NAND), vacuum field-emission transistor (VFET) and nanowire FETs have been investigated to understand their transport mechanism and to enhance electrical characteristics using TCAD simulation. In the V-NAND, effect of elliptical channel shape on memory characteristics in V-NAND has been investigated. Simulation results shows that program/erase efficiency was degraded in the elliptical channel shape. In program state, as the geometric aspect ratio (AR) decreases, non-uniformity of the channel E-field along the channel perimeter become larger and can degrade uniform injection of electrons during programing condition. Thus, due to non-uniformly localized trapped electron nearby major axis (longer axis) after the programing, threshold voltage (Vth) is mainly determined by the trapped electrons in the minor axis region. In erase state, as erasing time increases, hole injection into the major axis can reduce Vth, major and the channel current flowing across the major axis region becomes significant. The non-uniformity of E-field in the channel can also degraded the retention characteristics in V-NAND devices. The degradation of program/erase efficiency in elliptical channel can be mitigated by lowing program/erasing voltage. Moreover, retention characteristics of elliptical devices are degraded compared with that of the circular devices. The amount of charge loss along times in elliptical devices is higher compared with circular devices although the maximum E-field of the major axis regions in elliptical devices are higher than that of the circular devices. In nanoscale gate-all-around (GAA) vacuum field-emission transistors (VFETs), work-function engineering of three terminal electrodes was performed and analyzed their electrical variation characteristics using TCAD simulation. A lower gate work-function material can be useful to make thinner tunneling length and thus to reduce Vth for lower power operation. As we expected, the lower emitter work-function GAA VFETs can also provide a reduced Vth and reduce tunneling barrier height between the emitter and the vacuum channel resulting in the enhanced on-current ratio. Even though a pinned Vth behavior with various collector materials has been observed, a higher collector work-function can increase the tunneling barrier height nearby the collector side and mitigate carrier generation from the collector to vacuum, resulting in higher on-current with lower gate-leakage current. In the nanowire FETs (NWFETs), the analog figure-of-merits (FOMs) of junctionless (JL) NWFETs has been investigated regarding to the gate work-function variability (WFV) and random discrete dopant (RDD) using 3D TCAD simulation. For the JL-NWFET, it shows higher immune to WFV on analog FOMs while it was vulnerable to RDD due to inherently heavy channel-doping. Relatively week correlation between transconductance (gm) and gate-capacitance (Cgg) in JL-NWFET can lead to similar variation of the cut-off frequency (ft), compared to conventional NWFETs.