3차원 낸드 플래시 메모리를 위한 증분 스텝 펄스 프로그래밍(ISPP) 특성

Abstract

The demand of memory devices is increasing because electronics recently require more data processing than before. Semiconductor technology have been growing by Moore’s law. In past, central processing unit (CPU) was only embedded on computer but application units (APs) like CPUs are built into mobile and Internet of Things (IOT) devices to communicate between each other in addition to their original features. Despite the smaller size of AP than CPU, AP requires to store and process, so the memory system meets the demand. Storage is the element of computer to write and preserve non-volatile data and dynamic random access memory (DRAM) is to store volatile data, and to help AP and CPU to access data or address where data is written. In the storages so called non-volatile memory, NAND Flash memory device is in the spotlight because of their high degree of integration. NAND Flash memory has the merits: faster speed and higher density than the conventional storage, that is, hard disk drive (HDD). Since transistor concept was invented, semiconductor companies or manufacturers have focused on optimization of speed, power consumption, density and cost. Because NAND Flash memory is closely related to density and cost, 3D NAND Flash memory structure has been proposed as a game changer to increase density to overcome the scaling difficulty of 2D structure. Furthermore, as the technology of storing multi-bit has been proposed, it is possible to make NAND Flash memory dense and to reduce the cost. This technique is called Multi-Level Cell (MLC) technique. The width of threshold voltage Vth distribution of NAND Flash memory cells widens, when the binary information is written in the NAND Flash memory by using MLC technique. The widening of Vth distribution width, underprogram and overprogram problems are starting to emerge in MLC. Therefore, we use the scheme that is called incremental step pulse programming (ISPP) to make narrow the width of Vth distribution. In this thesis, we simulated the causal candidate to the variation of ISPP slope and measured Vth with respective to different Vstep, WL location for chip and wafer during ISPP and inspected whether ISPP slope is ideally 1 V/V or not, and if not, analyze why it is not.