A Delay Locked Loop with a Feedback Edge Combiner of Duty Cycle Corrector and A TIA with negative input-resistance for on-chip interconnect

Abstract

Firstly, A feedback edge combiner is proposed for the duty cycle corrector (DCC) of delay locked loop (DLL) to increase the range of allowed input duty cycle. The feedback edge combiner generates the rising edge of the DCC output at the rising edge of the input clock. It generates the falling edge of the DCC output at the rising edge of a feedback clock that is a half-period-delayed signal of the DCC output. A dual delay line DCDL (digitally controlled delay line) is used for the seamless boundary switching. The chip area of the DCDL is reduced by around 46% by employing the architecture of two short coarse delay lines followed by a fine phase mixer and a long coarse delay line in series instead of the architecture of two long coarse delay lines followed by a fine phase mixer. The measurements on the chip fabricated in a 65nm CMOS shows the allowed input duty cycle in the range from 20% to 80%, and the rms and p-p jitters of 2.69ps and 14.0ps at 2GHz and 1.2V, and the operating frequency range from 0.12GHz to 2.0GHz at 1.2V. The measured power consumption is 3.3mW/GHz at 1.2V. The chip area is 0.059mm2. Secondly, A negative input resistance (RIN) of TIA for on-chip interconnect increases the slew rate of the TIA input current; this increases the maximum data rate and reduces the TX equalizer power. RIN can be reduced down to -22.5Ω with the on-chip interconnect resistance of 500Ω without stability problems by maintaining the quality factor not exceeding 1.0. The transceiver chip was fabricated in a 65nm CMOS process. The best FOM (fJ/b/mm) at 2Gbps was measured to be 8.8 at RIN = -22.5Ω for the 10mm interconnect, and 7.0 at RIN = -20Ω for the 20mm interconnect. Compared to RIN = 40Ω, RIN = -20Ω increases the slew rates of both the TIA input current and the TIA output voltage by 23%, reduces the transmitter equalizer power by 51%, and reduces FOM by 18% with the 10mm interconnect. To reduce the PVT sensitivity of RIN, a replica circuit adjusts RIN to a value proportional to the on-chip interconnect resistance.