Characterization of Vertically Stacked Silicon Gate-All-Around Field-Effect Transistors using Simulation

Abstract

Bulk silicon FinFETs have been successfully adopted from 22- to 10-nm node in logic transistor technology. However, below 5-nm node, FinFETs would be suffered from extremely high fin aspect ratio, reduced pitch size, and increased parasitic resistance and capacitance, and then gate-all-around (GAA) nanosheet (NS) FETs were proposed to overcome the FinFETs technology. Unfortunately, due to process complexity of the NSFETs, these would also be suffered from process variations involving source/drain variations and diffusions of Ge and C induced by Si1-xGex and Si1-xCx epitaxies. Therefore, in this thesis, several process variation problems of the NSFETs are characterized and discussed using technology computer-aided design (TCAD) tools. DC/AC performances of sub 5-nm node NSFETs having realistic source/drain (S/D) shape are extensively analyzed according to S/D excess depth (TSD) using fully-calibrated 3-D TCAD simulation. Increasing the TSD reduces RC delay, but consumes more power due to significantly increased leakage currents of parasitic bottom transistor. These results are more sensitive to the TSD in PFETs than in NFETs due to S/D dopant diffusion effect. Thus, more elaborate S/D process (recess, epitaxy and anneal) is required for PFETs than NFETs. Threshold voltage (Vth) variations in sub 5-nm node NSFETs caused by Ge and C diffusion into NS channels using fully-calibrated 3-D TCAD simulation. Ge (C) atoms of Si1-xGex (Si1-xCx) source/drain (S/D) diffuse toward NS channels in lateral direction in PFETs (NFETs), and Ge atoms of Si0.7Ge0.3 stacks diffuse toward NS channels in vertical direction. Increasing Ge mole fraction of S/D in PFETs along with increasing compressive stress decreases boron dopants diffusing into NS channels, thus increasing the Vth of PFETs (Vth,p). However, the Vth,p decreases as Ge mole fraction of S/D is greater than 0.5 due to higher valence band energy (Ev) of NS channels. On the other hand, the Vth of NFETs (Vth,n) consistently increases as C mole fraction of S/D increases due to decreasing phosphorus dopants diffusing into NS channels. The Vth,p and Vth,n consistently decreases and increases, respectively, as Si/Si0.7Ge¬0.3 intermixing becomes severer because the valence and conduction band energies (Ec) of NS channels become higher. Furthermore, the Vth variations are more sensitive to Si/Si0.7Ge0.3 intermixing in PFETs than NFETs because the Ev is more sensitive to Ge concentration than the Ec. As a result, to optimize the Vth variations finely in sub 5-nm node NSFETs, Ge diffusion toward NS channels should be considered more than C diffusion toward NS channels.