Ultra-low-latency Soft-decision Decoder Architecture using OSD approach

Abstract

The ordered statistic decoding (OSD) algorithm for short-length linear block codes provides an attractive ML approaching performance, expected to be used for the ultra-reliable low latency communication (URLLC) at the next-generation wireless solutions. To find the corrected codeword among numerous candidates, however, the decoding process requires a considerable amount of computational costs, which need to be simplified to achieve low-latency processing. In this paper, we present several optimization schemes that relax the overall complexity of the state-of-the-art segmentation discarding algorithm. Without degrading the overall error-correcting capability, our approaches basically approximate the internal steps for calculating the segment boundary and the discarding threshold. The low-latency decoder architecture is also introduced to support the proposed simplified OSD algorithm. First, we introduce the stopping rule by applying the hard-decision BCH decoder to reduce the overall decoding latency. Furthermore, we use the optimized Gaussian elimination architecture with the overlapped sorter instead of using compute-intensive serialized Gaussian elimination. In addition, the reprocessing architecture is newly proposed to support the reprocessing operation. By using our simplified algorithm, the computational cost is reduced by 2x10^5 compared to the conventional OSD algorithm. The implementation results using 28-nm CMOS technology show that the proposed OSD architecture improves the decoding latency by 28.1 times compared to the baseline realization, achieving a throughput of 631 Mbps.