Many-Core Memory Controller Architectures

Abstract

In many-core systems, network size has been increasingly enlarged and they require wider bandwidth than before. Thus, network-on-chip (NoC) and memory with wide bandwidth such as 3D stacked DRAM have attracted much interest. However, as network size increases, network congestion causes more severe performance degradation. 3D stacked DRAM also does not fully utilize its increased bandwidth due to the peak power constraints of DRAM. This research proposes two kinds of memory controller architectures to solve these problems. The one solution is network congestion aware memory controller architecture which applies virtual channel concept and utilizes network congestion information in memory access scheduling. The other is peak power aware memory controller architecture which allows memory controllers to communicate with each other to perform budget sharing. Our experiments were performed on two kinds of systems: 5x5 NoC which consisted of 24 cores & a memory controller and 7x7 NoC which consisted of 45 cores & four memory controllers. When run on network congestion aware memory controller architecture, performance gains obtained were up to 131.5 % (from 16.8 % to 31.0 %) in memory utilization and 71.4 % in latency. In addition, gains drawn from peak power aware memory controller architecture were up to 11.7% (from 32.1 % to 35.8 %) in memory utilization and 18.8% in latency.