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Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
- Title
- Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
- Date Issued
- 2019-05-21
- Publisher
- IEEE
- ISSN
- 0195-623X
- Article Type
- Conference
- Citation
- 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), page. 37 - 42, 2019-05-21
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