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A 1.1µs 1.56Gb/s/mm^2 cost-efficient large-list SCL polar decoder using fully-reusable LLR buffers in 28nm CMOS technology
- Title
- A 1.1µs 1.56Gb/s/mm^2 cost-efficient large-list SCL polar decoder using fully-reusable LLR buffers in 28nm CMOS technology
- Authors
- KAM, DONG YUN; KONG, BYEONG YONG; LEE, YOUNGJOO
- Date Issued
- 2022-06-16
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Article Type
- Conference
- Citation
- 2022 IEEE VLSI Symposium on Technology and Circuits, 2022-06-16
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Related Researcher
- 이영주LEE, YOUNGJOO
- Dept of Electrical Enginrg