A Study on Performance Improvement of Compact CMOS Power Amplifiers in Millimeter-wave Band for Phased-array Frontend ICs

Abstract

Millimeter-wave (mm-Wave) frequencies have been attracting great attention in that they can provide opportunities for tens of giga-hertz broadband design and be used as another resource for modern saturated frequency bands. High-speed communication can be realized through a wide bandwidth, and mm-Waves are being actively studied as frequency bands for 5G, B5G, and next-generation communication, which is 6G. However, as the carrier frequency in the transmitter increases, the output power and gain of the transistor itself decrease, resulting in a decrease in effective isotropic radiation power (EIRP) and signal-to-noise ratio. Moreover, in the case of silicon-based complementary metal-oxide-semiconductor (CMOS) power amplifiers (PAs), which are excellent in terms of price and high-integration, it is difficult to achieve high output power in the mm-Wave due to low electron-hole mobility and low breakdown voltage of the Si-CMOS itself. Beamforming technology has been emerging as a key to providing sufficient EIRP, and to support this, transmitters should be designed in a phased-array architecture including multiple PAs. As the size of phased-array architecture increases, EIRP increases, but the number of front-end ICs increases, resulting in an increase in the total area of the transmitter. Therefore, in order to reduce the chip size of the transmitter, it is necessary to reduce the size of the element blocks constituting the front-end ICs (including PAs). We discuss the design and performance improvement of ultra-small mm-Wave PAs suitable for massive phased-array architecture in CMOS process. The basic role of a PA is to amplify the signal and output it with high power at a transmitter. Because PA deals with high power, PA consumes a lot of power, and large nonlinear signals are generated, degrading the linearity of PA. In particular, for high-speed communication, a wide and flat in-band operation must be supported over a large bandwidth. In this dissertation, three major works are explored toward the enhanced linearity, wideband operation, and enhanced output power with high efficiency, which are the most crucial performance in the mm-Wave CMOS PAs. First, we present the adaptive back-gate control to improve linearity. For high data rates, the 5G new radio system employs high-spectral-efficiency modulation schemes at mm-Wave frequencies, such as high-order quadrature amplitude modulation (QAM) and orthogonal frequency division multiplexing (OFDM), which have large peak-to-average power ratios (PAPRs). To avoid signal distortion in high-power operation with such large PAPR waveforms, PAs should be, in general, operated with a back-off power of around the PAPR at the cost of the average power-added efficiency (PAE). In addition, as channel bandwidth increases, the linearity of PA is dramatically degraded due to large intermodulation distortion. Therefore, the average input power should be backed off more than the PAPR, which results in PAE deterioration. In this work, we present a highly linear PA in 28-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS with adaptive back-gate bias control for 28-GHz 5G applications. Double-stacked-FET topology was adopted and upper and lower back-gate biases were adaptively controlled for input power level to improve the linearity without any impedance concerns. As a result, the back-off power was improved and the average PAE was enhanced by more than 3% in the system measurement results for single-carrier 64-QAM signals. Second, we present the wideband PA and E-band transmitter using a fourth-order transformer-based compact matching network. To achieve high data rates, a wide bandwidth transmitter is required, and PA plays an important role in determining the bandwidth of the transmitter. Impedance matching network containing a large number of inductors or capacitors can be adopted, however, it requires a large area and increases the complexity in terms of implementation. Instead, we use transformers (TFs) for compact and wide impedance matching. In two-stage PA with double-stacked-FET, three TFs (input, interstage, and output TF) were used for impedance matching and carefully designed to make PA flat and wide bandwidth using a small area. TFs with magnetic coupling act as fourth-order bandpass filters, which provide flat in-band properties and block out-band signals. In the transmitter, PA input is connected to the mixer output. Input TF of the PA with an additional shunt capacitor was designed to support the low quality factor (Q-factor) of the mixer output impedance. Due to the high Q-factor of the power stage input impedance, extra series inductive lines were used on both sides of interstage TF. These series inductors also help with wideband matching by lowering the coupling coefficient. The optimal output impedance of the power stage for high 1-dB compression output power (OP1dB) was matched to 50 ohm with output TF, which has a high coupling coefficient for maximum power delivery to the load. With the PA, we fabricated the E-band transmitter in 40-nm CMOS and measured the data rate. The measured maximum data rates were 48, 50, and 27 Gb/s for 16, 32, and 64-QAM signals, respectively, and the measured maximum signal bandwidth was 15.6 GHz for 16-QAM signal. Third, we present an F-band PA based on the stacked-FET topology to increase the output power. In order to increase the output power of the CMOS PA, a power cell with a large gate width transistor, a power combining technique, or a stacked-FET topology can be considered. At mm-Wave, the large power cell reduces the gain due to the large parasitic resistance and capacitance, which are particularly fatal for CMOS PAs with small maximum oscillation frequency. In addition, large gate resistance and gate-source/gate-drain capacitance lower the efficiency of the PA. The power combining technique can effectively increase the output power, but the gain of the PA itself cannot be increased because the overall power is divided in the input and merged in the output. In particular, except for the impedance matching part of the first input port and the last output port, since several PAs with the same area is used, a large area of the chip size is required. The stacked-FET topology increases the output power by using a core transistor configuration similar to cascode structure to increase the supply voltage of the output. The stacked-FET topology has an overall area smaller than that of the power combining technique, and the gain and output power are simultaneously increased. Because of these advantages, this study proposes a stacked-FET topology as a solution to increase the power in CMOS PAs in mm-Wave frequencies. Also in the high frequency, impedance matching between stacked FETs should be required to recover the reduced stacking efficiency. Details of stacked-FET topology on the operating frequency and impedance matching between stacked-FETs, including real losses, were analyzed, and a compact and high-efficient triple-stacked-FET power amplifier was designed based on this in F-band. The PA achieves a maximum PAE of 18.6%, which are, to the authors’ best knowledge, the highest efficiency compared to state-of-the-art CMOS PAs in the F-band.