3차원 낸드 플래시 메모리의 문턱전압분포를 좁히기 위한 개선된 ISPP 방식

Abstract

As the fourth industrial revolution is underway based on the internet of things (IOT), artificial intelligence (AI), and robot engineering technology, the demand for advanced computation and big data storage using semiconductors have increased. Memory semiconductors responsible for storing information are divided into volatile memory, which loses data without a power supply, and non-volatile memory, in which semipermanent charge storage is possible. NAND flash memory is a representative non-volatile memory. It stores information by controlling the threshold voltage (Vth) of the device and is used in the universal serial bus (USB), solid state drive (SSD), and servers. The biggest advantage of NAND flash memory is its high integration, low cost, and good retention characteristics. NAND flash technology exhibits a trend of increasing the density of a chip. The structure of NAND flash memory changed from two-dimensional (2-D) to three-dimensional (3-D) to reduce the side effects of scaling and increase the density through stacking the word line (WL) layers. Although the 3-D structure effectively increases the density of a NAND flash chip, the importance of scaling and multi-level cell (MLC) technology is growing as the stacking process gradually approaches its limit. Scaling and MLC technology effectively increase the density of a chip, but there are some problems. First, the Vth distribution width becomes wider because of increased cell-to-cell interference and decreased number of electrons per one-volt Vth shift. Second, the margin of Vth distribution between program states (reliability margin) decreases as increasing bits per cell for MLC technology. The wide width and narrow reliability margin of the Vth distribution make it difficult to distinguish the stored data in each memory cell and cause errors. Thus, narrowing the Vth distribution is important for persistent scaling and error reduction. In this study, the improved incremental step-pulse programming (ISPP) scheme to narrow Vth distribution by reducing the number of abnormal program cells (APCs) has been proposed. APCs, excessively programmed cells whose Vth overlaps with the next program state, increase the Vth distribution width. As the programming step voltage (Vstep) decreases immediately before the target cells pass the nth program-verify level (PVn), the difference between Vth and PVn decreases, causing a reduction in the number of APCs. Therefore, in the improved ISPP scheme, the Vstep is selectively reduced at the target ISPP steps, at which most cells are predicted to be programmed in the next ISPP step for each program state. As a result, the increase in the total number of program pulses is minimized, and the Vth distribution width decreases considerably. This work used chip-level measurement equipment to extract the Vth data and other parameters. Then, the improved ISPP scheme was applied to the NAND flash memory chip to confirm its effectiveness. Consequently, scaling and larger bit density is feasible by applying improved ISPP scheme, resulting in high-capacity NAND flash memory.