4.7-GHz Cryo-CMOS Parametric Amplifier at mK Temperature for Superconducting Quantum Computers

Abstract

In this paper, we present the Cryo-CMOS parametric amplifier for superconducting quantum computers. The operating principle, power gain, and noise factor of the parametric amplifier were expressed mathematically through circuit analysis. To overcome the limitations of existing research, on-chip port isolation is realized, and the core layout structure is modified for better isolation. The proposed parametric amplifier was implemented in a 65-nm CMOS process and its area is 0.64𝑚𝑚². The fabricated chip was embedded on the PCB for cryogenic experiments. At 20mK, measured minimum noise temperature was 61 K at 𝑓₁Ｆ = 4.494GHz, with a maximum power gain of 13.8 dB at 𝑓₁Ｆ = 4.569GHz and a noise temperature of 80.6 K at the same frequency. The port isolation performance was measured better than -47 dB in a room temperature on-wafer environment and -13 dB in a 4K PCB environment. The 𝐼𝑃₁㏈ of the circuit was measured as -57𝑑𝐵𝑚 at 4K. Measurement and simulation results were compared. After then, an analysis of the curvature of the noise temperature was performed. Performances considering system uncertainty were also presented. The limitations of this study were discussed.