Resistive Memory Devices and Arrays for Neural Network Hardware Implementation

Abstract

Living in the deep learning era, artificial intelligence (AI) has become an indispensable technology for human beings, widespread in our lives. Thanks to the advances in deep neural network algorithms, state-of-the-art AI has achieved unprecedented success in real-world applications such as biomedical, pattern recognition, signal classifications, etc. However, based on the von Neumann architecture, conventional digital computers cannot withstand the ever-increasing sizes and complexities of neural networks and tasks, thereby facing a severe limitation in energy efficiency. In addition, with the advent of the internet of things (IoT), the location of AI service approaches from the cloud server to the power-constraint edge devices. In this regard, developing brain-inspired neuromorphic computing, i.e., hardware neural networks (HNNs), is essential. There have been myriad studies on artificial neural networks in crossbar arrays consisting of novel resistive memory devices to achieve brain-like energy efficiency and considerable performance gain. As the resistive device-based crossbar architecture can be operated in an analog and massively parallel manner, it has shown great potential to achieve a significant acceleration in AI computation. Although various synapse devices have been studied for the past ten years, they were only able to meet some of the key requirements for universal HNN applications. Since the requirements such as linearity conductance change, retention, operation speed, multi-level conductance, and low-power operation conflict with each other, it is challenging to implement a highly integrated nanoscale synapse device. This dissertation contains practical approaches to developing resistive devices and arrays for hardware implementation of neural networks. To realize HNN implementation, I focused on finding device requirements of HNN during inference and training operations through various neural network simulation tools, such as MATLAB, C++, and SPICE. At the same time, I developed different synaptic devices, i.e., fixed resistor and resistive switching memory (RRAM), and utilized those devices depending on their purpose of use: inference and training of the hardware. To scale out the studies on developing a single unit device, I also fabricated 32 x 32 crossbar arrays and analyzed them using a custom-made switching matrix printed circuit board. Moreover, I proposed several ideas to improve the training performance of HNN by using non-ideal devices. Finally, the successful implementation of inference HNN was demonstrated, and the performance improvements in HNN training, even with the device's non-idealities, were presented. This thesis aims to bridge the gap between the realistic resistive device and neuromorphic AI hardware implementation by delivering research results through a combination of device, array, and network simulation works.