A Wide-Range Locking Multi-Phase Delay Locked Loop

Abstract

In this thesis, a 40-to-700MHz locking multi-phase DLL, an analysis and design methodology of resistor-based phase error averaging for multiphase generation, and a 110MHz-to-1.4GHz locking 40-phase all-digital DLL are proposed.Firstly, a delay matrix and a gradual switching of shunt capacitors are proposed for wide-range-locking multi-phase DLL. With a two-dimensional structure, the delay matrix achieves multiphase generation at high-frequency. The delay matrix employs a novel resistor network to improve the phase linearity by error averaging. For the wide-frequency-range lock, shunt capacitors in delay cells are gradually switched by a bias control scheme. The DLL was implemented in a 0.13？？m CMOS process. Monotonous 40 phases were achieved in a lock range of 40MHz to 700MHz. measured INL was 1.1LSB and DNL was 0.47LSB. The peak-to-peak jitter was 12ps, and power consumption was 43mW at the supply voltage of 1.2V.Secondly, a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation are performed. By taking the signal transition time into account, the analysis leads a different result from those of previously reported analyses which commonly state that more averaging achieves better linearity. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18？？m CMOS, generates monotonous 32 phases, showing an INL of +0.27/-1.0LSB and a DNL of +0.37/-0.27LSB at 1.2GHz, and an INL of +0.23/-1.57LSB and a DNL of +0.44/-0.44LSB at 1.6GHz.Finally, an all-digital DLL is designed to generate low jittery 40 phases in a continuous lock range of 110MHz-to-1.4GHz. The DLL is driven by dual loops ？V one for phase lock and the other for offset calibration. The two loops are updated by a chopping PD which adaptively extracts valid information for each loop, one at a time. For the optimal 1b delay resolution in the entire lock range, a piecewise profiling of delay line is also proposed. The DLL, fabricated in a 0.13？？m CMOS, reveals the best linearity performance compared with previously reported works, showing a DNL of less than 0.3LSB and a INL of less than 0.8LSB in the entire lock range up to 1.4GHz. With the piecewise-fitted delay line, the amount of peak-to-peak and rms jitters induced by DLL operation is controlled to be less than 0.825-percent and 0.2-percent of the clock period, respectively. Power consumption was 74.4mW at the supply voltage of 1.2V.