Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors

Abstract

The optimal inner spacer length (L-IS) for each layer in nanosheet (NS) field-effect transistors (FETs) was investigated using a technology computer-aided design (TCAD) simulation. Although gate-all-around (GAA) NS channels show excellent electrical characteristics, the parasitic channels formed in the punchthrough stopper (PTS) region show poor electrical characteristics. Further, the PTS region is susceptible to source/drain recess depth (T-SD) variations, which can cause considerable punchthrough current (I-PT). Hence, owing to the difference in the electrical properties of the NS channels and PTS region, the gate length (L-g) must be optimized for each channel. This study proposes a novel scheme that can selectively adjust the L-g by stacking Si/SiGe layers with different germanium mole fractions. Consequently, shortening the L-IS at the bottom alone can considerably decrease the I-PT without a large increase in the gate capacitance (C-gg). In the NSFETs with T-SD = 4 nm, the OFF-state current (I-off) decreased by 24.0%, while the C-gg increased by 5.2%. When comparing the performance of the NSFETs with the different L-IS combinations at the same I-off, the RC delay was improved by up to 19.5% (T-SD = 4 nm) and 5.3% (T-SD = 0 nm) compared to the NSFETs with a uniform L-IS. The proposed scheme is highly feasible as it does not require additional process steps. Additionally, since the gate controllability of each channel can be adjusted separately, the proposed scheme enables the performance optimization of the NSFETs.