Investigation of Electrothermal Characteristics in Silicon Forksheet FETs for Sub-3-nm Node

Abstract

In this study, the self-heating effect (SHE) of sub-3-nm node forksheet (FS) field-effect transistors (FETs) and nanosheet (NS) FETs were systematically analyzed using a fully calibrated technology computer-aided design (TCAD) simulation. The electrothermal characteristics of FSFETs differ from those of NSFETs owing to a unique structural feature, namely, the SiN wall. The SiN wall of FSFETs reduces the gate metal, enhancing the electrical characteristics; however, the thermal characteristics deteriorate as the SiN wall inhibits heat dissipation. The evaluation of electrothermal properties using power-delay product and thermal resistance indicated that FSFETs were superior to NSFETs at the single device level; furthermore, in ring oscillators (RO), FSFETs are faster and have lower average power consumption and maximum lattice temperature than NSFETs. Owing to low maximum lattice temperature variations, FSFETs were less impacted by the SHE-induced hot carrier injection (HCI) and bias temperature instability (BTI) lifetime degradation at iso-frequency. This study, therefore, validates FSFETs targeting sub-3-nm nodes considering SHE and shows the superiority of FSFETs over NSFETs.