Microwave-Reduced Graphene Oxide with Doping towards VLSI Interconnect

Abstract

As CMOS technology nodes scale down to the nanometer range, the need for innovative interconnect solutions has become increasingly apparent. Copper damascene technology, an industry standard for over a decade, is grappling with rising resistance, self-heating (SH), and electromigration (EM) challenges. To sustain CMOS scaling, exploring alternatives to copper is imperative. Graphene-based interconnects, known for their exceptional electrical and thermal conductivity as well as inherent EM resistance, have emerged as a promising solution [1-3]. However, seamlessly integrating graphene into CMOS fabrication processes remains a formidable challenge. In this study, we investigate a graphene-based interconnect technology using microwave-assisted reduction of graphene oxide (GO). Fully reduced GO (rGO) exhibits conductivity akin to graphene, and GO can be easily deposited and patterned through spin-coating and plasma etching. If reduction can be accomplished within the heat budget of CMOS backend-of-line (BEOL) processes, it offers a cost-effective interconnect solution. We prepared a spin-coating solution from GO produced via the Hummer method, resulting in a 20nm-thick GO film. Low temperature microwave irradiation transformed the GO film into rGO, verified by the removal of oxidized functional groups, as indicated by XPS and Raman Spectra in Fig. 1(a) and (b). The rGO film was patterned as Hall bars with metal contacts, as depicted in Fig. 1(c), and their transport properties were evaluated. We will also address the potential doping process to enhance the rGO film's conductivity.