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A 2.35 Gb/s/mm^2 (7440, 6696) NB-LDPC decoder over GF(32) using memory-reduced column-wise trellis min-max algorithm in 28nm CMOS technology

Title
A 2.35 Gb/s/mm^2 (7440, 6696) NB-LDPC decoder over GF(32) using memory-reduced column-wise trellis min-max algorithm in 28nm CMOS technology
Authors
JEONGWON, CHOELEE, YOUNGJOO
Date Issued
2023-06-12
Publisher
IEEE
URI
https://oasis.postech.ac.kr/handle/2014.oak/121333
Article Type
Conference
Citation
2023 Symposium on VLSI Technology and Circuits (VLSI), 2023-06-12
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이영주LEE, YOUNGJOO
Dept of Electrical Enginrg
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