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Reinforcement Learning-based Analog Circuit Optimizer using gm/IDfor Sizing

Title
Reinforcement Learning-based Analog Circuit Optimizer using gm/IDfor Sizing
Authors
KANG, SEOKHYEONGChoi, MinjeongChoi, YoungchangLee, Kyongsu
Date Issued
2023-07-09
Publisher
Institute of Electrical and Electronics Engineers Inc.
Abstract
Designing analog circuits incurs high time costs because designers must consider numerous design variables or trade-off relationships of circuit performance based on a lot of knowledge and experience. To reduce design time, various machine learning methods have been used to optimize analog circuits by learning the correlation between the device size and the circuit performance. However, it is difficult to train the correlation because of its high non-linearity and wide design space. In this paper, this study proposes a new framework to optimize analog circuit designs by combining reinforcement learning (RL) and the sensitivity analysis with gm/ID sizing, which is more intuitive for interpreting circuit performance. Furthermore, the universal value function approximator (UVFA), previously proposed in RL, is modified more simply to make it easier to find the target design. Additionally, the dataset is rearranged and sampled by the criteria that are established based on the principle of circuit operation, which helps to orient the agent to learn the circuit operation. Using the proposed methods, we optimize three types of differential amplifiers with common mode feedback circuits and obtain the best circuit design. Compared to baseline, we find the optimal point using modified UVFA, and moreover, reduce the number of iterations by 42.2%, 39.5%, and 37.5%, respectively, for the three test cases.
URI
https://oasis.postech.ac.kr/handle/2014.oak/121908
Article Type
Conference
Citation
60th ACM/IEEE Design Automation Conference, DAC 2023, 2023-07-09
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