DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, Haena | - |
dc.contributor.author | Yoon, Jongho | - |
dc.contributor.author | Kim, Dohun | - |
dc.contributor.author | Kwon, Eunji | - |
dc.contributor.author | Oh, Tae-Hyun | - |
dc.contributor.author | Kang, Seokhyeong | - |
dc.date.accessioned | 2024-03-06T08:10:53Z | - |
dc.date.available | 2024-03-06T08:10:53Z | - |
dc.date.created | 2024-02-22 | - |
dc.date.issued | 2023-04-17 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/122625 | - |
dc.description.abstract | Numerous network compression methods have been proposed to deploy deep neural networks in a resource-constrained embedded system. Among them, block-circulant matrix (BCM) compression is one of the promising hardware-friendly methods for both acceleration and compression. However, it has several limitations; (i) limited representation due to the structural characteristic of circulant matrix, (ii) limitation of the compression parameter, (iii) need to specialize the dataflow for BCM-compressed network accelerators. In this paper, rank-enhanced and highly-pruned block-circulant matrices compression (RP-BCM) framework is proposed to overcome these limitations. RP-BCM comprises two stages: Hadamard-BCM and BCM-wise pruning. Moreover, a dedicated skip scheme is introduced to processing element design for exploiting high-parallelism with BCM-wise sparsity. Furthermore, we propose specialized dataflow for a BCM-compressed network on a resource-constrained FPGA. As a result, the proposed method achieves parameter reduction and FLOPs reduction for ResNet-50 in ImageNet by 92.4% and 77.3%, respectively. Moreover, the proposed hardware design achieves 3.1× improvement in energy efficiency on the Xilinx PYNQ-Z2 FPGA board for ResNet-18 on ImageNet compared to the GPU. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 | - |
dc.relation.isPartOf | Proceedings -Design, Automation and Test in Europe, DATE | - |
dc.title | FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 | - |
dc.citation.conferenceDate | 2023-04-17 | - |
dc.citation.conferencePlace | BE | - |
dc.citation.title | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 | - |
dc.contributor.affiliatedAuthor | Oh, Tae-Hyun | - |
dc.contributor.affiliatedAuthor | Kang, Seokhyeong | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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