Configurable Energy-Efficient Lattice-Based Post-Quantum Cryptography Processor for IoT Device

Abstract

This thesis presents an energy-efficient lattice-based crypto-processor for IoT devices supporting both encryption and decryption of Homomorphic Encryption and Post-Quantum Cryptography algorithms. To improve the performance, the chip employs a reconfigurable architecture on a unified number system, a Residue Number System (RNS) to effectively reduce the size of modulo, and a scheduling for pipelining. The implemented chip in 28nm CMOS achieves state-of-the-art power efficiencies both in Homomorphic Encryption and Post-Quantum Cryptography.