Analysis, Design, and Generation Techniques for Cost-Efficient Single-Ended Short-Reach Transceivers

Abstract

This thesis presents the transceiver designs and automatic layout generation techniques aimed at reducing the various costs associated with single-ended links for short-reach applications. The thesis consists of two main parts: a study on the transceiver with relaxed impedance matching, and a study on the 1/N-rate receiver front-ends generation using layout generation techniques. Theoretical and quantitative analyses demonstrate that it is possible to improve the performance of voltage-mode transmitters by relaxing the impedance matching without causing a serious signal integrity problem. Based on these analyses, an inverter-based transceiver is suggested that ensures excellent signal integrity through relaxed impedance matching while simultaneously overcoming various single-ended noises by enlarging the output swing and the eye size. The proposed inverter driver offers a large output swing and good area efficiency, distinguishing it from the conventional source-series termination driver. By taking the advantage of a large signal swing, the receiver design can be simplified with only four slicers and latches, reducing both area and design complexity. In measurements, the transmitter achieved a large output swing of 850 mV, which is 50.4 % larger than the conventional source-series termination transmitter, and also achieved the eye openings of 440 mV and 234 mV at 16 Gb/s (-2.7 dB) and 20 Gb/s (-8 dB), respectively. Even in the presence of significant switching noise of about 100 mV, the in-situ eye at the receiver was measured 114 mV at 16 Gb/s with -7.4 dB loss. This thesis also introduces the software that significantly shortens the physical design time for 1/N-rate wireline receiver front-ends. The physical layouts of various receiver front-ends were software-generated in four different CMOS technology nodes (28 nm, 40 nm, 65 nm, and 90 nm) with four different front-end architectures targeting various data rates. In the post-layout simulation, the receiver front-ends generated within a second by the software achieved nearly the same performances as the manually-designed receiver front-ends that require more than about 30 hours of design time. For demonstration, the generated 8 Gb/s full-rate, 10 Gb/s half-rate, 12 Gb/s, and 20 Gb/s quarter-rate receiver front-ends were fabricated with a manually-designed feed-forward equalization transmitter. The transceivers were measured with the data rate up to 20 Gb/s while consuming 1.39 pJ/b at the channel loss of -9.2 dB. The transceiver with software-generated receiver achieved the highest data rate per area as well as the smallest area among the relevant prior arts while reducing the physical design time of the receiver front-end by more than 140,000 times.