Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells

Abstract

We present an efficient design technique for implementing the optimal ramped gate soft-programming for curing the over-erased flash EEPROM cells. The technique does not rely on any I-V model but is solely based upon using the actual cell performance data and enables accurate prediction of programming time, given supply current (I-S). The full utilization of available supply current renders the programming speed much faster and also enables reliable multi-bit soft-programming, The ramped gate scheme induces a strong self-con vergence of the simultaneously up-shifted threshold voltages regardless of their initial values or the variations of the shift speed from cell to cell.