DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, SH | - |
dc.contributor.author | Lee, SK | - |
dc.contributor.author | Kim, B | - |
dc.contributor.author | Park, HJ | - |
dc.contributor.author | Sim, JY | - |
dc.date.accessioned | 2016-03-31T07:36:22Z | - |
dc.date.available | 2016-03-31T07:36:22Z | - |
dc.date.created | 2016-02-22 | - |
dc.date.issued | 2014-09 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.other | 2014-OAK-0000031731 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/13814 | - |
dc.description.abstract | An energy-efficient 3 Gb/s current-mode interface scheme is proposed for on-chip global interconnects and silicon interposer channels. The transceiver core consists of an open-drain transmitter with one-tap pre-emphasis and a current sense amplifier load as the receiver. The current sense amplifier load is formed by stacking a PMOS diode stage and a cross-coupled NMOS stage, providing an optimum current-mode receiver without any bias current. The proposed scheme is verified with two cases of transceivers implemented in 65 nm CMOS. A 10 mm point-to-point data-only channel shows an energy efficiency of 9.5 fJ/b/mm, and a 20 mm four-drop source-synchronous link achieves 29.4 fJ/b/mm including clock and data channels. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.title | Current-Mode Transceiver for Silicon Interposer Channel | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1109/JSSC.2014.2336213 | - |
dc.author.google | Lee, SH | - |
dc.author.google | Lee, SK | - |
dc.author.google | Kim, B | - |
dc.author.google | Park, HJ | - |
dc.author.google | Sim, JY | - |
dc.relation.volume | 49 | - |
dc.relation.issue | 9 | - |
dc.relation.startpage | 2044 | - |
dc.relation.lastpage | 2053 | - |
dc.contributor.id | 11082511 | - |
dc.relation.journal | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.9, pp.2044 - 2053 | - |
dc.identifier.wosid | 000341564200016 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 2053 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 2044 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 49 | - |
dc.contributor.affiliatedAuthor | Lee, SK | - |
dc.contributor.affiliatedAuthor | Kim, B | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.contributor.affiliatedAuthor | Sim, JY | - |
dc.identifier.scopusid | 2-s2.0-84906949164 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 15 | - |
dc.description.scptc | 18 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.description.isOpenAccess | N | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Memory interface | - |
dc.subject.keywordAuthor | on-chip link | - |
dc.subject.keywordAuthor | silicon interposer | - |
dc.subject.keywordAuthor | transceiver | - |
dc.subject.keywordAuthor | wireline | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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